Random access memories (RAMs) are used in numerous applications to store digital data. A RAM generally includes multiple individually-addressable memory locations within a memory cell array for storing data. Each memory location typically stores several individual bits (e.g., a byte) of data. A RAM may include a number of ports for writing data to and reading data from its memory cell array. Typically, each port includes data input/output lines, address lines, a write enable line, and an output-enable line.
To read a byte of data from a memory location of the RAM, an address is applied on the address lines of a port, and a pulse is provided on the port's output-enable line. The application of the pulse on the port's output-enable line causes the byte of data stored at the memory location identified by the address to be provided on the data input/output lines of the port.
To write a byte of data to a memory location of a RAM, the byte of data is provided on the data input/output lines of a port, an address (which uniquely identifies the memory location to which data is to be written) is provided on the port's address lines, and a pulse is applied on the port's write-enable line. The application of the pulse on the write-enable line causes the byte of data on the data input/output lines to be written to the memory location identified by the address on the address lines.
Typically, the write-enable line and the data input/output lines are connected to a large number of capacitive components within the memory cell array of the RAM. The pulse applied on the write-enable line therefore must be of a minimum amplitude and duration to provide a sufficient amount of charge onto the line to bring it to a voltage level sufficient to write the data to the memory cell array. Because of this minimum amplitude and pulse-width requirement, the write-enable line of a RAM is said to be level sensitive. Additionally, to ensure that the correct data is written to the memory cell array in response to such a pulse, the data signals must also be applied on the data input/output lines for a minimum period time to charge or discharge the lines properly.
FIG. 1 shows an example of a prior art circuit in which a dual-port RAM 102 (including ports A and B) is employed to implement a first-in first-out buffer (FIFO) 100. As shown in FIG. 1, the port A of the RAM 102 includes data input lines 108a, address lines 106a, and a write-enable line 118a. Similarly, the port B of the RAM 102 includes data output lines 108b, address lines 106b, and an output enable line 118b. In addition to the dual port RAM 102, the FIFO 100 includes a write pointer 104a and a read pointer 104b. As shown in FIG. 1, an output of the write pointer 104a is applied on the address lines 106a of the port A, and an output of the read pointer 104b is applied on the address lines 106b of the port B. The pointers 104a-b are generally implemented using counters.
In the FIG. 1 example, the write enable line 118a and the output enable line 118b are active high. That is, data on the data input lines 108a of the RAM 102 is written to a memory location identified by an address on the address lines 106a in response to a logic-high signal being applied on the write-enable line 118a, and data from a memory location of the RAM 102 identified by an address on the address lines 106b is provided on the data output lines is 108b in response to a logic-high signal being applied on the output-enable line 118b. The pointers 104a-b increment in response to falling edges of signals applied on their clock inputs and are interlocked so as not to violate a FIFO implementation as known in the art.
The FIFO 100 includes data input lines 112, a write line 110, data output lines 116, and a read line 114. When the WRITE signal (applied on the write line 110) transitions from a low state to a high state, the data (Data.sub.-- in) present at the data input lines 112 is written to the address of the RAM 102 identified by the write pointer 104a. When the WRITE signal subsequently transitions from a high state to a low state, the write pointer 104a increments its output by one. Similarly, when the READ signal (applied on the read line 114) transitions from a low state to a high state, the data at the address identified by the read pointer 104b is presented on the data lines 116 of the FIFO 100. When the READ signal subsequently transitions from a high state to a low state, the read pointer 104b increments its output by one. Therefore, the write pointer 104a effectively points to the next memory location of the RAM 102 that will be written when the WRITE signal next transitions from a low state to a high state, and the read pointer 104b effectively points to the next memory location of the RAM 102 that will be read when the READ signal next transitions from a low state to a high state.
As should be appreciated from the foregoing, each pulse of the WRITE signal both: (1) causes the data on the data lines 112 to be written to the memory location pointed to by the write pointer 104a, and (2) causes the write pointer 104a to increment by one after this data has been written to the RAM 102. Similarly, each pulse of the READ signal both: (1) causes the data at the memory location pointed to by the read pointer 104b to be provided on the data output lines 116, and (2) causes the read pointer 104b to increment by one after this data has been so provided.
FIG. 2 shows an example of how the pointers 104a-b may each point to one of "m" possible memory locations in a memory cell array 200 of the RAM 102 (FIG. 1). Each of the "m" memory locations in the FIG. 2 example includes storage space for "n" data bits. The one of the "m" memory locations currently pointed to by the write pointer 104a is identified in FIG. 2 by an arrow 202, while the one of the memory locations currently pointed to by the read pointer 104b is identified by an arrow 204.
As mentioned above, due to the relatively large capacitance of the write enable line 118a and the data lines 108a of the RAM 102, for the data on the data lines 112 to be correctly written to the memory location currently pointed to by the write pointer 104a, the pulse in the WRITE signal must be of a minimum amplitude and duration, and the data must applied on the data lines 108a for a minimum period of time. The input capacitance of the clock input of the write pointer 104a, however, is much lower than that of the write enable line 118a and the data lines 108a, and the write pointer 104a is edge sensitive (rather than level sensitive). Therefore, a pulse in the WRITE signal may cause the write pointer 104a to increment even though the pulse is not of a sufficient amplitude and/or duration to cause data to be written to the memory location pointed to by the write pointer 104a.
The fact that the write enable line 118a is level sensitive and the write pointer 104a is edge sensitive can cause problems in at least two situations: (1) when an intentionally produced pulse in the WRITE signal is of a sufficient amplitude to cause the write pointer 104a to increment but (e.g., due to noise) is not of a sufficient amplitude and duration to properly write data to the RAM 102, and (2) when noise is introduced on the write line 110 that is of an amplitude sufficient to cause the write pointer 104a to increment when no write to the FIFO 100 was intended.
FIGS. 3-4 and 5-6 illustrate, respectively, the first and second of the two above-mentioned problematic situations as they might occur when writing data to memory locations of the FIFO 100 shown in FIGS. 1-2. In the examples shown in FIGS. 3-6, the memory array 200 of the FIFO 100 includes four memory locations, each being four bits wide.
FIGS. 3 and 5 are timing diagrams each showing the relationship between the data (Data.sub.-- in), the WRITE signal, and the value of the write pointer 104a over a particular time interval. FIGS. 4A-D illustrate, respectively, the contents of the memory cell array 200 at the times t.sub.0 -t.sub.3 of the timing diagram shown in FIG. 3. FIG. 4E illustrates a situation in which the read pointer 104b points to a memory location that contains stale data (i.e., data left over from a previous pass through the FIFO 100) as a result of the events illustrated in FIGS. 3 and 4A-D. FIGS. 6A-D illustrate, respectively, the contents of the memory cell array 200 at the times t.sub.0 -t.sub.3 of the timing diagram shown in FIG. 5. FIG. 6E illustrates a situation in which the read pointer 104b points to a memory location that contains stale data as a result of the events illustrated in FIGS. 5 and 6A-D.
As shown in FIGS. 3-6, each high pulse in the WRITE signal that is of a sufficient amplitude and duration causes the data (Data.sub.-- in) to be written to the memory location of the FIFO 100 pointed to by the write pointer 104a at the time the pulse occurs. Also, the falling edges of the pulses in the WRITE signal cause the write pointer 104a to increment by one.
In FIG. 3, between the times t.sub.1 and t.sub.2, the pulse 302 in the WRITE signal is not of a sufficient amplitude and duration to cause the data (B0 . . . 3!) to be written to the memory location pointed to by the write pointer 104a (i.e., memory location "1" of the memory cell array 200), but is of a sufficient amplitude that its falling edge causes the write pointer 104a to increment by one. Because the pulse 302 does not cause data to be written to memory location "1," any stale data stored at this memory location during a previous pass through the FIFO 100 is not overwritten. The presence of stale data in the FIFO 100 is illustrated in FIGS. 4C-E by the question marks in memory location "1" of the memory cell array 200.
In FIG. 5, a noise pulse 502 is introduced between adjacent high pulses in the WRITE signal. The noise pulse 502 does not cause any data to be written to the memory location pointed to by the write pointer 104a, but is of a sufficient amplitude that its falling edge causes the write pointer 104a to increment by one (as shown in FIG. 6C). Stale data therefore remains at the memory location skipped by the write pointer 104a (i.e., memory location "1") due to the noise pulse 502. The presence of stale data in the FIFO 100 is illustrated in FIGS. 6C-E by the question marks in memory location "1" of the memory cell array 200.
As noted above, FIGS. 4E and 6E illustrate situations in which the read pointer 104b points to memory locations that contain stale data as a result of the events illustrated, respectively, in FIGS. 3 and 4A-D and FIGS. 5 and 6A-D. In the examples shown, when the system reads data from the memory location "1" of the memory cell array 200, it is expected that this memory location will contain the data (B0 . . . 3!). Instead, stale data is read from memory location "1." In either situation, with the prior art system shown in FIGS. 1-2, there is no way of determining that the data read from memory location "1" is stale. Therefore, in these examples, the fact that stale data is read from memory location "1" is not recognized by the system. This undetected reading of stale data may result in incorrect data being output by the FIFO 100, thereby causing system errors.